Integrated circuits are often designed on computer systems with design tools using hardware description languages (HDL). Examples of HDL include Verilog and VHDL. During the circuit design process, timing analysis of the circuit frequently identifies points in the circuit design where logic signal delays need to be implanted for the circuit to function properly.
Currently, logic signal delays are hand-coded using delay gates of a synthesis library that is used with a HDL design tool. Broadly speaking, a synthesis library is a software library describing logic gates in a manner closely associated with a fabrication process technology. Fabrication process technology or the more commonly used expression “process technology” is a term of art encompassing the various processes for manufacturing an integrated circuit and is usually associated with the average feature size of the integrated circuit that can be manufactured. An example of a fabrication process technology is 0.13 micron technology.
If it is desirable to transfer an IC design to a smaller fabrication process technology, a synthesis library associated with the smaller fabrication process technology must be used with an HDL design tool. Because the smaller fabrication process technology differs from when the circuit was originally designed, logic signal delay requirements between logic gates will also be different from the original circuit design. Consequently, logic signal delays must be redesigned and implanted into the IC design for the circuit to function properly with the smaller fabrication process technology.
The process of redesigning logic signal delays can be time consuming and is prone to human error. Therefore a method is required for generating logic signal delays in an integrated circuit design which automatically adjusts when the integrated circuit design is transferred across synthesis libraries incorporating different IC fabrication process sizes.